SiC power semiconductor devices has begun to be used in industries such as power generation and transmission systems that control large amounts of electrical power, industrial robots, automobiles, railways, and information and communication devices. The important factor for the spread of these devices is to reduce the manufacturing cost of the SiC wafers that are the core elements of power devices. Furthermore, the higher speed and parallel processing are needed in the SiC wafer machining process.

A SiC wafer is hard and brittle material that is difficult to process. Planarization of SiC wafers has thus far been performed by grinding or polishing. Grinding is a single wafer process with low mass production efficiency, and polishing is a batch type process that can process multiple wafers at once. However, the processing speed is slower than the mass production processing of silicon wafers, so it takes six or more times longer to process the same number of wafers per unit time. The SiC wafer diameter is poised to increase from 6 inches to 8 inches. As mass production scales increase due to market expansion in the future, processing technology that can produce SiC wafers even more efficiently will be needed.

Researchers in AIST developed lapping technology that achieved high-speed planarization of SiC wafers in collaboration with Mizuho Co., Ltd. and Fujikoshi Machinery Corp. In particular, 12 times the polishing speed was achieved in the previously slow mirror finishing process. The new batch processing technology demonstrated the comparable surface quality to that of a mirror grinding process using the single wafer processing method.