The Grid Technology Research Center (GTRC) and the Advanced Semiconductor Research Center (ASRC) of the National Institute of Advanced Industrial Science and Technology (AIST), an independent administrative institution, have studied the validity of the low density parity check code (LDPC) in collaboration with the NEC Electronics Corp. (NEC-E) and the Tokyo Electric Power Co. (TEPCO). The LDPC is an error correcting code in the signal configuration of “10GBASE-T” standard of ethernet transmission at 10 Gb/s using twisted pair wire. The collaboration team succeeded in verifying the validity of the LDPC by using the AIST SuperCluster.

The LDPC was proposed at the IEEE Standardization Committee (IEEE802.3an) held at Portland, U.S. in July 2004, for the incorporation to the IEEE standards, jointly by NEC-E, TEPCO and AIST. The proposal was approved by the unanimous vote of attendants. This will contribute to accelerated incorporation of the 10GBASE-T to the IEEE Standards.

The standardization of 10GBASE-T has been studied separately by NEC-E, TEPCO, Evolvable systems Research Institute, Inc. (ERI), a venture firm approved by AIST, and AIST, from their own positions. However, as these organizations are claiming the same LDPC for error correcting code, it was decided to make a joint proposal by NEC-E, TEPCO and AIST.

The 10GBASE-T is a network standard for network machine to tie up LAN, interconnecting server machines and future connection of personal computers, and is expected to create a gigantic market in the future. However, the standardization of 10GBASE-T is not in progress because no formality is available for approving error correcting code of transmission signal. The error correcting code adopted by the IEEE Standardization Committee (IEEE802.3an) as one of IEEE Standards is named LDPC. The code is best suited for error correcting code of 10GBASE-T, with high decoding capability for data transmission error and fast processing based on parallel operation of computing program. For adopting the LDPC as IEEE standard, the IEEE Standardization Committee (IEEE802.3an) requests to demonstrate the absence of error floor through the computer simulation. While the simulation takes computing time as long as seven and a half years with an ordinary processor according to the estimation by the NEC-E. The computing time has been shortened to two weeks owing to the program optimization by the AIST and by the use of the AIST SuperCluster. In this way, it has been demonstrated that the LDPC code contains no error floor. The result was reported at the IEEE Standardization Committee (IEEE802.3an), and the proposal for incorporating the LDPC code to the IEEE standards was accepted.

The error correcting code constitutes an important prerequisite for developing LSI for 10 Gb/s ethernet. The decision to approve the LDPC code as error correcting code will accelerate the development of ethernet-compatible LSI and make the implementation of 10GBASE-T more realistic. It is expected that the LDPC code is used for the backbone of IP communications and the Internet Data Center (IDC) for a time, and for the interconnection of PCs in the future, to form a gigantic market.

While at present, the 10 Gb/s ethernet based on optical fiber is used for the wide area communications, the 10GBASE-T ethernet standard using the twisted pair wire has certain merits, such as no need for optical communications module, low cost instrumentation, and easy installation work including cable handling. Moreover, the ethernet based on twisted pair wire is most widely used in offices and homes holding a large-sized market, and its implementation is urgently wanted. At present, the IEEE Standardization Committee (IEEE802.3an) is inquiring into the standardization of 10GBASE-T.

However, the fast transmission system such as 10GBASE-T is vulnerable to noises, causing communication errors. It is necessary, therefore, to find out and correct errors in the transmission line by using a new standard for error correcting code. In case of 10GBASE-T, signals of higher frequency than before pass through the ethernet cable, and hence, are readily affected noises and the attenuation of higher frequency components, increasing the occurrence of transmission errors. In order to solve the problem of transmission error, it is necessary to decode the original data by use of error correcting code. With the 10GBASE-T, more powerful error correcting code is needed. However, the IEEE Standardization Committee (IEEE802.3an) had no error correcting code to be adopted as a new standard.

So far, four organizations NEC-E, TEPCO, ESRI and AIST proposed independently to standardize the 10GBASE-T from their own positions: the NEC-T claimed adopting the LDPC code based on the single carrier system, while TEPCO, ESRI and AIST on the basis of the multiple carrier system, since March 2004. Since these claims have a common ground of using the LDPC code for the error correcting code, they decided to promote the standardization of the LDPC code through a joint effort.

At the IEEE Standardization Committee (IEEE802.3an), a format for error correcting code named LDPC code was proposed by the Intel Corporation in November 2003. The LDPC has high error correcting capability and is suited for fast processing based on parallel operation. However, the LDPC has not yet been adopted as standard, because the absence of error floor has not been corroborated. The NEC-E developed a program to verify the absence of error floor, and GTRC/ASRD-AIST and NEC-E successfully demonstrated the validity of LDPC code through a large-scale computer simulation using the AIST SuperCluster.

In order to prove the absence of error floor in the LDPC code, it is necessary to do a computer simulation with very small transmission error, or bit error rate as small as 10-12, and for verifying the absence of error floor adequately, the simulation requires to provide enormous amount of data, feeding data bit string as massive as 1014 bits into the communication path. According to the earlier computer simulation by the NEC-E, the simulation with an ordinary PC (Xeon 3.06 GHz) would take computing time as long as seven and a half years.

Through the optimization of the program by the AIST and the parallel processing using 256 processors of computer nodes in the AIST SuperCluster (a cluster system of two-way SMP nodes with Xeon 3.06GHz processor, peak performance 1.57 Tflop/s), the computing time was successfully reduced to two weeks. It is demonstrated, therefore, that the LDPC code does not include error floor.

The NEC-E, TEPCO and AIST reported the results at the IEEE Standardization Committee (IEEE802.3an) held at Portland, U.S. on July 14, 2004, and proposed to incorporate the LDPC code to the IEEE standards. Next day, July 15, a vote was taken on the motion, and the LDPC code was approved for the standard unanimously.

[1] IEEE = Institution of Electrical and Electronic Engineers