The Nanoelectronics Research Institute (NERI) of the National Institute of Advanced Industrial Science and Technology (AIST), one of independent administrative institutions, succeeded in realizing a new device technology of 4-terminal drive using two independent gates, in the form of double-gate MOSFET, which is expected to be a transistor of the new generation. The original 4-terminal drive features including optional threshold voltage control were systematically verified using sub 0.1-μm device of 80 nm gate length. (1 nm = 10^-9 m = 1/1,000,000,000 m). The study will lead the way to the materialization of innovative LSI, capable of flexible and dynamic control for optimum power consumption and operation speed.

Novel features installed on an ultimate MOSFET

The double-gate MOSFET, originally proposed in 1984 as "XMOS" by the Electrotechnical Laboratory (ETL) under the Agency for Industrial Science and Technology (former AIST) has been expected to be the most advanced transistor giving a breakthrough to the scaling limit due to increasing leak current and short channel effects in the ordinary single- gate MOSFET. However, the conventional double-gate MOSFET with combined two gates held at an identical voltage has to work in a 3-terminal mode. The newly developed double-gate MOSFET can be driven in a genuine 4-terminal mode with independent two gates controlled separately. This means that the transistor operation speed can be controlled to an optimum, and the power loss caused by leak current during standby is substantially nullified. That is, the new technology will open the way to the implementation of the ultra-low power LSI characterized by optimum power control without sacrificing operation speed. The 4-terminal driven double-gate MOSFET can also be regarded as a MOSFET equipped with an arithmetic operation feature based on independent two-input capability. A single device with such as a circuit function indicates the possibility of extensively reduction of the number of devices in VLSIs.

Wide use 4-terminal driven double gate technology developed

A technological breakthrough in this work is the development of technology for fabrication of separate double gates MOSFET with 4-terminal drive capability based on micro-fabrication compatible with the present semiconductor technology. The very thin silicon (Si) channel of standing fin form was fabricated by the anisotropic wet etching dependent on the crystal face orientation, which had been originally developed by the AIST. As a result, the fin channels with an ideal rectangular cross-section were successfully constructed. A pair of polycrystalline Si gates, independent from each other and sandwiching the very thin fin channel, were manufactured through the chemical mechanical polishing (CMP) technology. The micro-fabrication technologies developed in this study, anisotropic wet etching and fine CMP, are compatible with the present semiconductor technologies, and may readily be led to the practical application. The incorporation of new capabilities to the conventional double-gate MOSFET is expected to bring out a significant innovation in the Si integrated circuits.

Flexible threshold voltage controllability of the 4-terminal driven double gate MOSFET verified systematically

With the fabricated 4-terminal driven double gate MOSFET of 80 nm gate length, it was demonstrated that the threshold voltage Vth of the transistor could be varied by changing one of the gate voltages. This function is an epoch-making success in reducing power consumption at a higher threshold voltage, and at the same time, in ensuring high operation speed at a lower threshold voltage. It was also verified with the fabricated device of 13-nm thick Si fin that the thinner the Si-fin channel was, the higher effectiveness would be achieved both in threshold voltage control and in suppressing short channel effects. Furthermore, it was experimentally substantiated in the synchronized 4-terminal drive mode with an off-set voltage between two gate voltages that the short channel effects could be suppressed the most effectively with the optional control of V_th.

The present work succeeded in implementing the 4-terminal drive to the double gate MOSFET expected as the coming generation transistor opens a way to innovative expansion of function of the transistor. The further efforts will be paid to the creation of the new IC technology based on the optimal utilization of the 4-terminal driven double gate MOSFET.

The results of this study will be announced in the International Electron Devices Meeting 2003 (IEDM2003) to be held December 8~10, 2003 at Washington, DC. This is the second disclosure of new electron devices from the NERI, AIST at the IEDM following that in 2002. In regard to this work, three patent applications have been filed.

Figure. Evolution of the MOSFET: (a) Single gate MOSFET, (b) Conventional (fin-type) double gate MOSFET, and (c) Four-terminal double gate MOSFET