The Nanoelectronics Research Institute (NERI) of the National Institute of Advanced Industrial Science and Technology (AIST) has succeeded in the development of a 1T FeRAM wherein one-bit memory cell consists of only one transistor, and has verified its superior performance characteristics.

• A major step ahead toward achieving the next-generation ferroelectric memory
  The commercially available FeRAM that is also on the way of further development has two transistors and two ferroelectric capacitors (2T2C) or one transistor and one ferroelectric capacitor (1T1C) in the one bit memory cell. It therefore requires a large area for the one bit, making it difficult to achieve ultra-Gbit advanced integration.
  
  Since the 1T FeRAM consists of only one ferroelectric gate field-effect transistor (FET), the area required for one bit memory cell is extremely small. It therefore holds great promise of serving as an ultra-Gbit FeRAM with a hyper-advanced level of integration. However, the problem of 1T FeRAM is that the data retention time was short (about one day at best), dimming any prospects of its practical application. (In Japan, several companies have been engaged in research without being able to surmount this difficulty.)
  
  The 1T FeRAM developed at AIST has a proven data retention time of around 12 days from data entry. (Even after 10⁶ seconds "1" and "0" data can be read out and the current ratio is of more than six orders in magnitude.) This success was the breakthrough that opened up, for the first time, the way for the practical application of the 1T FeRAM.


• Development of an advanced thin-film formation technology using laser ablation technique to achieve a stack consisting of a high-quality ferroelectric and a buffer layer.

The technical breakthrough in the development of the new technology for stacking the ferroelectric and buffer layer lies in the fact that strontium, bismuth and tantalum oxide (SrBi2Ta2O9) has been used for the ferroelectric and a hafnium (Hf) composite oxide material for the buffer layer (between the silicon substrate and the ferroelectric). Laser ablation is a superior technique for expressing the intrinsic properties of materials to permit the formation of a high-quality laminate film. We have also succeeded in forming a dense amorphous film using a new material, enabling us to reduce leakage currents in the insulating buffer layer. The development of these technologies has led to a dramatic increase in the data retention time.

The newly developed ferroelectric memory has resolved the problem of poor data retention and thus opens up a promising prospect for further improvements in performance, including a reduction in memory operating voltage. Apart from the use of the ferroelectric for memory applications, further development is envisioned that will lead to its use in reconfigurable logic circuits.

The NERI of AIST took part in the Next-Generation Ferroelectric Memory Research and Development Project of the Ministry of Economy, Trade and Industry within the period from fiscal 1999 to 2001, during which a part of the fundamental laser processing technology was developed.

 

Intensive research is taking place worldwide to develop a large-capacity, high-speed non-volatile memory to replace the DRAM. A ferroelectric random access memory (FeRAM) using a ferroelectric is already mass-produced and available on the market, albeit on a small scale. As can be seen in Fig. 1 (left), one bit of this conventional FeRAM consists of a capacitor and a transistor. The fact that in this system, the charge amount stored in the capacitor is read out directly is a limiting factor in the pursuit of further miniaturization (large scale circuit integration). Although this conventional FeRAM is seen as a promising high-capacity memory to replace the DRAM it offers no room for further capacity expansion.

The AIST has developed the 1T FeRAM (Fig. 1 (right)) which uses a ferroelectric film instead of the gate insulating film of the single field-effect transistor. The area required for a single cell is merely the space occupied by the transistor. In this memory, the semiconductor surface conductor channel opens and closes in response to the status of the electric polarization stored by the ferroelectric film (Fig. 2). The data memory status is read out as a function of the presence or almost absence of a flowing electric current when a voltage is applied between the drain and source electrodes on both ends of the conductor channel. Its structure is simple and its area is small. Furthermore, there is no limitation in future device miniaturization in the sense of the operational principle, that is a great advantage compared to the conventional FeRAM. In this manner, the 1T FeRAM holds great promise as the ultimate semiconductor memory capable of further miniaturization (higher integration). In other words, it offers scope for capacity expansion. However, there has still been the technical difficulty of achieving both a high-quality semiconductor surface and a high-quality ferroelectric. The most important problem to be solved has been the short data retention time.

The AIST has resolved these problems by developing the thin-film stacking technology needed for a high-quality ferroelectric and buffer layer (between the ferroelectric and semiconductor silicon) by using laser ablation technique. This has paved the way for a capacity increase for the 1T FeRAM beyond the Gbit level.

Fig.1 Structural Comparison of the Conventional FeRAM (left) and the 1T FeRAM (right)

Fig. 2 Structure of the 1T FeRAM

(1) Development of a technique for forming a thin-film stack consisting of a high-quality ferroelectric and a buffer layer using a laser ablation process

In the laser ablation process, a pulsed laser beam is focused on the target. Since evaporation takes place only in the irradiated part the quality of the material constituting the target will have a direct bearing on the quality of the thin film deposited in the substrate. It is therefore easy to obtain a high-quality thin film by this method. In addition to the particular features of this laser ablation technique we have also tried to optimize the pressure and gas kind in the growth vessel as well as the substrate temperature. Furthermore, we have used a new composite hafnium (Hf) oxide to form a stable amorphous buffer layer. As a result, we were able to develop the 1T FeRAM by achieving a dense, low-leakage-current stack of the ferroelectric and buffer layer.

(2) Verification of long-term data retention capability

We produced a 1T FeRAM on a silicon substrate (Fig. 3 left and right). The gate insulation film ferroelectric consists of SrBi₂Ta₂O₉. Data are written in when positive/negative voltage pulses are applied to the gate electrode. When a voltage VD is applied to the drain electrode after applying a positive 6V pulse an adequate current ID will flow in the conductor channel (defined as information "1"). In contrast, the current ID after applying a negative 6V pulse is negligible when VD is applied (defined as information "0" (Fig. 4). After entering the data, we then measured the data retention characteristics (Fig. 5). The x-axis gives the time after data entry and the y-axis the readout current ID. Both are expressed on a logarithmic scale. If the readout current ratio of the information "1" to "0" is large, it is easy to distinguish the "1" and "0" states. This current ratio therefore serves as a good indicator of the data retention performance. Immediately after the data entry (after 1 second) this ratio is in the order of 7 digits. After 106 seconds (approximately 12 days) this ratio has still a very large value, with 6 digits being maintained. When this ratio is 2 digits it is possible to distinguish the "1" and "0" states. By extrapolating this tendency it is found that a data retention time in the order of a year can be achieved.

 

Fig. 3 Photograph of 1T FeRAM. The cross-section view by a scanning electron mocroscope (left) and the top view by an optical light microscope (right).

Fig. 4 Readout characteristics of information "1" and "0" stored in the memory.

Fig. 5 Retention characteristics of information "1" and “0” stored in the memory.