The High Density SI Group of Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, one of independent administrative institutions, has succeeded in the development of high density fine wiring interposer for connecting LSI chips to implement ultra-high speed and ultra-high density packing in collaboration with a technological research association, Association of Super-Advanced Electronics Technology (ASET). (See Fig. 1.)

The performance of LSI chips is advancing by leaps and bounds year after year, as demonstrated by the clock frequency of CPU chips surpassing 3GHz. However, the clock frequency for signal transmission over external paths such as those from CPU chips to memory is as low as 500MHz. Owing to the difference in transmission rate by a factor ranging from a few to dozens, the processing rate of the entire system fails to cope with the increasing volume of information. For this reason, the clock frequency for the transmission over the linkage between LSI chips is requested to be as fast as that for LSI chips. One of technologies to meet this requirement is high density system packing technology, also termed as System-In Package (SiP), where multiple LSI chips are combined to operate as if it is a single LSI chip. In the present R&D work, a high density fine wiring interposer for 3D connection of solid build-up of LSI chips has been developed successfully for the first time in the world. (Fig. 2)

Fig. 1. Pictures of High Density Connection Interposer

Fig. 2. A Cross-section of High Density Wiring Interposer

The high density fine wiring interposer is characterized by high performance signal wiring structure (strip line construction), which ensures 10Gbps transmission rate suited for optoelectronic high speed transmission module, and by 50ω characteristic impedance which allows matching with existing peripheral devices. The structure has been realized by using photosensitive polyimide (relative permittivity = 3), a low permittivity organic insulator material, for an insulating layer between metal wirings. With this insulator, it has become possible to reduce the minimum wire width from 50μm (1μm = 10^-6m) or so in the conventional printed circuit board technology to as fine as 7.5μm. The connection with LSI chips is designed with fine bumps of 20μm pitch to be fitted to the LSI chip direct connection (flip chip linkage) forming process. In the fabrication of high density fine wiring interposer, the use of high resolution photosensitive polyimide insulation layer has made it possible to realize wiring linkage holes (peer holes) through the optical transfer (lithography) process alone, to simplify the process extensively. This will reduce the cost of manufacturing process in the commercialization.

Details of this R&D work will be reported at the 2003 International Conference on Solid-State Devices and Materials (SSDM2003) to be held at the Keio Plaza Hotel, Tokyo, September 16~18, 2003.

This study has been carried out as a part of the Next Generation Semiconductor Devices & Processes Basic Technology Program “Ultra-High Density Electronic System Integration (SI) Technology” sponsored by the New Energy and Industrial Technology Development Organization (NEDO).

In relation to the results of this study, three patent applications have been filed.