HOME > Research Results > 2003 > AIST team develops genetic algorithm-based method to adjust clock timing that allows power consumption to be halved in high-speed LSIs: Adjusted clock timing provides enhanced clock frequencies and reduced design times

Update(MM/DD/YYYY):07/24/2003

AIST team develops genetic algorithm-based method to adjust clock timing that allows power consumption to be halved in high-speed LSIs: Adjusted clock timing provides enhanced clock frequencies and reduced design times

(Translation of AIST press release on June 11, 2003)

Highlights

Power consumption by a GHz digital large-scale integrated circuit (LSI) was cut by 54% by reducing power supply voltage to two-thirds the previous level, through clock timing adjustment using a genetic algorithm (GA).
By adjusting the clock timing, working clock frequencies were enhanced by up to 25%.
The clock timing was adjusted by periods of less than 1 second, so the method could also be applied to mass-production systems.
By using design methods that incorporate the adjusted clock timing, design times can be reduced by 20%.

Summary

The Advanced Semiconductor Research Center (ASRC) of the National Institute of Advanced Industrial Science and Technology (AIST) and the Association of Super-Advanced Electronics Technologies (ASET), which are working together on the Semiconductor MIRAI Project, have developed a GA-based method to adjust clock timing that allows enhanced working clock frequencies and halved power consumption by high-speed LSIs operating at the GHz level.

With high-speed LSIs operating at over 1 GHz, clock skew (mistimed clock signal transmission) reduces the proportion (operational yield) of LSIs that can operate in line with the design specifications, which in turn leads to increased prices. Moreover, high-speed clock operations generate problems with high power consumption.

Against this backdrop, the research team developed a method that generated clock frequencies higher than specified in the target design (enhanced by up to 25%) and functioned in two types of LSI circuits developed for the purpose (memory test pattern production equipment including a 1-GHz ALU and a 1-GHz multiplier). The team also reduced power consumption by 54% by reducing the power supply voltage from the standard 1.2V to 0.8V. The research showed that adjusted clock timing allows the effective operation of LSIs that suffer from incorrect timing due to reduced power supply voltage.

In addition, the research has clearly demonstrated that timing design is easier if the circuit design assumes clock timing will be adjusted using this method. As a result, design times can be reduced by 20% (evaluated on the design process for a high-speed memory DDR-SDRAM controller).

In order to facilitate the application of this method for adjusting clock timing, the research team plans to develop practical-use LSI chips that operate at 3 GHz and experiment with reduced power consumption in mobile computers with clock frequencies of several hundred MHz.

Details of this research were presented at the 2003 Symposium on VLSI Circuits, held at the Rihga Royal Hotel Kyoto in Kyoto, 12–14 June 2003. A number of patents are being filed on the research.

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